Model Simulation FPGA ASIC [50 MHz] time (FF+LUT) SLC / [ns] comb.+reg. / [ns] gcd-bhv 0.52 us not synthesizable not synthesizable gcd-bhvc 2.72 us not synthesizable 2-, 1<, 1/=, 3rg, 4st 457+504=961 / 20.0 gcd-bfsm 2.72 us 2-, 1=, 1<, 3rg, 3st 2-, 1<, 1/=, 3rg, 3st (51+171) 108 / 9.9 401+510=911 / 19.4 gcd-rtl1 7.28 us 1-, 3rg, 6st 1-, 3rg, 6st (55+77) 50 / 10.8 469+517=986 / 19.8 gcd-rtl2 5.08 us 1-, 3rg, 5st 1-, 3rg, 5st (52+77) 48 / 10.8 413+518=931 / 19.9 gcd-rtl3 2.72 us 1-, 1<, 3st 1-, 1<, 3rg, 3st (51+95) 58 / 17.0 623+511=1134 / 20.0 gcd-rtl4 2.72 us 2-, 3rg, 3st 2-, 3rg, 3st (51+137) 78 / 12.6 469+507=976 / 19.9 gcd-rtl5 2.72 us 2-, 1/=, 3rg, 3st 2-, 1/=, 3rg, 3st (52+96) 58 / 8.0 408+507=915 / 20.0 ------------------------------------------------------------------------ [100 MHz] [25 MHz] gcd-bhvc not synthesizable 473+504=977 / 31.1 gcd-bfsm (51+171) 108 / 9.4 474+510=984 / 30.8 gcd-rtl1 (55+77) 50 / 9.7 366+517=883 / 32.4 gcd-rtl2 (52+77) 48 / 10.0 365+517=882 / 32.3 gcd-rtl3 (51+95) 58 / 14.6! 421+507=928 / 40.0 gcd-rtl4 (51+137) 78 / 9.0 421+507=928 / 29,0 gcd-rtl5 (52+96) 58 / 7.6 425+507=932 / 26.9 '+' - adder '-' - subtractor '=' - comparator equal '/=' - comparator not equal '>=' - comparator greater-equal '<' - comparator less 'rg' - registers 'st' - states ======================================================================== ALU styles FPGA ASIC LUT (SLC) / [ns] gates / [ns] gcd_alu0 1-, 1/=, 1< 1-, 1