test_skeem Project Status (04/27/2016 - 13:10:32)
Project File:	Lab_3.xise	Parser Errors:	No Errors
Module Name:	test_skeem	Implementation State:	Programming File Generated
Target Device:	xc3s1200e-5fg320	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	4 Warnings (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	58	17,344	1%
Number of 4 input LUTs	47	17,344	1%
Number of occupied Slices	53	8,672	1%
Number of Slices containing only related logic	53	53	100%
Number of Slices containing unrelated logic	0	53	0%
Total Number of 4 input LUTs	85	17,344	1%
Number used as logic	47
Number used as a route-thru	38
Number of bonded IOBs	31	250	12%
Number of BUFGMUXs	1	24	4%
Number of RPM macros	4
Average Fanout of Non-Clock Nets	2.74

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Wed Apr 27 13:10:02 2016	0	0	2 Infos (0 new)
Translation Report	Current	Wed Apr 27 13:10:07 2016	0	0	0
Map Report	Current	Wed Apr 27 13:10:12 2016	0	1 Warning (0 new)	2 Infos (0 new)
Place and Route Report	Current	Wed Apr 27 13:10:24 2016	0	2 Warnings (0 new)	2 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Wed Apr 27 13:10:27 2016	0	0	6 Infos (0 new)
Bitgen Report	Current	Wed Apr 27 13:10:31 2016	0	1 Warning (0 new)	0

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Out of Date	Wed Apr 27 13:11:05 2016
WebTalk Log File	Out of Date	Wed Apr 27 13:10:32 2016

Date Generated: 04/27/2016 - 13:11:59