io_module Project Status (05/13/2015 - 13:17:51)
Project File:	Nexsys2_test.xise	Parser Errors:	No Errors
Module Name:	io_module	Implementation State:	Programming File Not Generated
Target Device:	xc3s1200e-5fg320	Errors:
Product Version:	ISE 14.7	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	36	17,344	1%
Number of 4 input LUTs	28	17,344	1%
Number of occupied Slices	33	8,672	1%
Number of Slices containing only related logic	33	33	100%
Number of Slices containing unrelated logic	0	33	0%
Total Number of 4 input LUTs	49	17,344	1%
Number used as logic	28
Number used as a route-thru	21
Number of bonded IOBs	20	250	8%
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	2.44

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Wed May 13 10:57:46 2015
Translation Report	Current	Wed May 13 10:59:09 2015
Map Report	Current	Wed May 13 10:59:19 2015
Place and Route Report	Current	Wed May 13 10:59:43 2015
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report	Current	Wed May 13 10:59:47 2015
Bitgen Report	Out of Date	Tue May 12 21:53:58 2015

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Log File	Current	Wed May 13 13:17:51 2015

Date Generated: 05/13/2015 - 13:17:51