| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
0 |
126,800 |
0% |
|
| Number of Slice LUTs |
0 |
63,400 |
0% |
|
| Number of occupied Slices |
0 |
15,850 |
0% |
|
| Number of LUT Flip Flop pairs used |
0 |
|
|
|
| Number of bonded IOBs |
4 |
210 |
1% |
|
| IOB Flip Flops |
1 |
|
|
|
| Number of RAMB36E1/FIFO36E1s |
0 |
135 |
0% |
|
| Number of RAMB18E1/FIFO18E1s |
0 |
270 |
0% |
|
| Number of BUFG/BUFGCTRLs |
1 |
32 |
3% |
|
| Number used as BUFGs |
1 |
|
|
|
| Number used as BUFGCTRLs |
0 |
|
|
|
| Number of IDELAYE2/IDELAYE2_FINEDELAYs |
0 |
300 |
0% |
|
| Number of ILOGICE2/ILOGICE3/ISERDESE2s |
1 |
300 |
1% |
|
| Number used as ILOGICE2s |
1 |
|
|
|
| Number used as ILOGICE3s |
0 |
|
|
|
| Number used as ISERDESE2s |
0 |
|
|
|
| Number of ODELAYE2/ODELAYE2_FINEDELAYs |
0 |
|
|
|
| Number of OLOGICE2/OLOGICE3/OSERDESE2s |
0 |
300 |
0% |
|
| Number of PHASER_IN/PHASER_IN_PHYs |
0 |
24 |
0% |
|
| Number of PHASER_OUT/PHASER_OUT_PHYs |
0 |
24 |
0% |
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHCEs |
0 |
96 |
0% |
|
| Number of BUFRs |
0 |
24 |
0% |
|
| Number of CAPTUREs |
0 |
1 |
0% |
|
| Number of DNA_PORTs |
0 |
1 |
0% |
|
| Number of DSP48E1s |
0 |
240 |
0% |
|
| Number of EFUSE_USRs |
0 |
1 |
0% |
|
| Number of FRAME_ECCs |
0 |
1 |
0% |
|
| Number of IBUFDS_GTE2s |
0 |
4 |
0% |
|
| Number of ICAPs |
0 |
2 |
0% |
|
| Number of IDELAYCTRLs |
0 |
6 |
0% |
|
| Number of IN_FIFOs |
0 |
24 |
0% |
|
| Number of MMCME2_ADVs |
0 |
6 |
0% |
|
| Number of OUT_FIFOs |
0 |
24 |
0% |
|
| Number of PCIE_2_1s |
0 |
1 |
0% |
|
| Number of PHASER_REFs |
0 |
6 |
0% |
|
| Number of PHY_CONTROLs |
0 |
6 |
0% |
|
| Number of PLLE2_ADVs |
0 |
6 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of XADCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
0.75 |
|
|
|