tester Project Status (04/11/2016 - 17:47:21) | |||
Project File: | lab2_proj.xise | Parser Errors: | No Errors |
Module Name: | tester | Implementation State: | Synthesized |
Target Device: | xc3s1200e-5fg320 |
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No Errors |
Product Version: | ISE 14.7 |
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2 Warnings (1 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 35 | 8672 | 0% | |
Number of Slice Flip Flops | 45 | 17344 | 0% | |
Number of 4 input LUTs | 69 | 17344 | 0% | |
Number of bonded IOBs | 21 | 250 | 8% | |
Number of GCLKs | 1 | 24 | 4% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mon Apr 11 17:47:21 2016 | 0 | 2 Warnings (1 new) | 2 Infos (1 new) | |
Translation Report | Out of Date | Mon Apr 11 17:17:57 2016 | 0 | 0 | 0 | |
Map Report | Out of Date | Mon Apr 11 17:18:02 2016 | 0 | 1 Warning (1 new) | 3 Infos (0 new) | |
Place and Route Report | Out of Date | Mon Apr 11 17:18:14 2016 | 0 | 2 Warnings (2 new) | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | Mon Apr 11 17:18:17 2016 | 0 | 0 | 6 Infos (0 new) | |
Bitgen Report | Out of Date | Mon Apr 11 17:18:22 2016 | 0 | 1 Warning (1 new) | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Wed Mar 16 10:46:45 2016 | |
WebTalk Log File | Out of Date | Mon Apr 11 17:18:24 2016 |