test_skeem Project Status (02/15/2016 - 12:06:43)
Project File:	Lab_1.xise	Parser Errors:	No Errors
Module Name:	test_skeem	Implementation State:	Programming File Generated
Target Device:	xc3s1200e-5fg320	Errors:	No Errors
Product Version:	ISE 14.7	Warnings:	6 Warnings (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	76	17,344	1%
Number of 4 input LUTs	63	17,344	1%
Number of occupied Slices	68	8,672	1%
Number of Slices containing only related logic	68	68	100%
Number of Slices containing unrelated logic	0	68	0%
Total Number of 4 input LUTs	96	17,344	1%
Number used as logic	63
Number used as a route-thru	33
Number of bonded IOBs	17	250	6%
Number of BUFGMUXs	2	24	8%
Average Fanout of Non-Clock Nets	2.67

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Mon Feb 15 12:05:54 2016	0	3 Warnings (0 new)	3 Infos (0 new)
Translation Report	Current	Mon Feb 15 12:06:01 2016	0	0	0
Map Report	Current	Mon Feb 15 12:06:08 2016	0	1 Warning (0 new)	2 Infos (0 new)
Place and Route Report	Current	Mon Feb 15 12:06:29 2016	0	1 Warning (0 new)	2 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Mon Feb 15 12:06:34 2016	0	0	6 Infos (0 new)
Bitgen Report	Current	Mon Feb 15 12:06:42 2016	0	1 Warning (0 new)	0

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Out of Date	Mon Feb 15 00:25:05 2016
WebTalk Log File	Current	Mon Feb 15 12:06:43 2016

Date Generated: 02/15/2016 - 12:06:43